Split Latency Allocator: Process Variation-Aware Register Access Latency Boost in a Near-Threshold Graphics Processing Unit
by
 
Pal, Asmita, author.

Title
Split Latency Allocator: Process Variation-Aware Register Access Latency Boost in a Near-Threshold Graphics Processing Unit

Author
Pal, Asmita, author.

ISBN
9780438056442

Personal Author
Pal, Asmita, author.

Physical Description
1 electronic resource (39 pages)

General Note
Source: Masters Abstracts International, Volume: 57-06M(E).
 
Advisors: Koushik Chakraborty Committee members: Amanda Lee Hughes; Sanghamitra Roy.

Abstract
Over the last decade, Graphics Processing Units (GPUs) have been used extensively in gaming consoles, mobile phones, workstations and data centers, as they have exhibited immense performance improvement over CPUs, in graphics intensive applications. Due to their highly parallel architecture, general purpose GPUs (GPGPUs) have gained the foreground in applications where large data blocks can be processed in parallel. However, the performance improvement is constrained by a large power consumption. Likewise, Near Threshold Computing (NTC) has emerged as an energy-efficient design paradigm. Hence, operating GPUs at NTC seems like a plausible solution to counteract the high energy consumption. This work investigates the challenges associated with NTC operation of GPUs and proposes a low-power GPU design, Split Latency Allocator, to sustain the performance of GPGPU applications.

Local Note
School code: 0241

Subject Term
Computer engineering.

Added Corporate Author
Utah State University. Computer Engineering.

Electronic Access
http://gateway.proquest.com/openurl?url_ver=Z39.88-2004&rft_val_fmt=info:ofi/fmt:kev:mtx:dissertation&res_dat=xri:pqm&rft_dat=xri:pqdiss:10829245


Shelf NumberItem BarcodeShelf LocationShelf LocationHolding Information
XX(694886.1)694886-1001Proquest E-Thesis CollectionProquest E-Thesis Collection