Quality of Service (QoS) is commonly associated with network data transmissions or CPU scheduling. This dissertation supplies an interconnect architecture which bridges the gap in QoS support between the computer peripherals supplying data and the Operating System applications which process this data. The aim of this research is to provide QoS support for the PCI bus, guaranteeing a minimal throughput rate for devices sharing a resource-limited data path within the desktop PC architecture. Providing QoS support at the interconnect level requires two complementary modifications to existing architectures. The first modification enables devices to separate their data stream into individual channels. Each channel represents a data stream belonging to a particular application, and has its own QoS parameters. These channels are queued in a local buffer until the interconnect is ready to transmit them. The second modification addresses the scheduling component required to ensure that QoS requirements are enforced on a per-channel basis. The interconnect design presented within this dissertation applies both of the modifications detailed above to an existing bus architecture, the PCI bus. The resulting architecture, called the MINT, is evaluated through software simulation, and the MINT simulation results are compared to standard PCI bus behaviour. The design principles of MINT are architecturally neutral, and can be applied to a wide range of interconnect standards, including both serial and parallel implementations. Simulation results show that QoS guarantees, when applied to individual datastreams, can successfully provide both resource reservation and deadline control.