Parallel computer systems built with multiprocessors have become ubiquitous in all high-performance computing domains. Performance gains due to the parallel processing will come from the proliferation of processing cores, leading to hundreds of cores integrated on a single chip. The Network-on-Chip (NoC) design paradigm overcomes the problems of wire delays and limited communication bandwidth by replacing conventional shared buses with an interconnection network that allows simultaneous communication and thereby increasing system performance.

Silicon photonic devices are compatible with standard CMOS technology and use photons instead of electrons to bring light onto a chip. Photonic links feature high data transmission rates and low propagation losses, especially suitable for replacing long-distance wires. In the wavelength-division multiplexing technique, several dozen wavelengths share a waveguide without interference and can be modulated and received individually. Recent advancements in NoC designs have leveraged the benefits of silicon photonics. However, many photonic NoC architectures require 3D-stacking technology and more dies to place the additional photonic devices, resulting in higher manufacturing costs.

In this dissertation, we study how to design high-performance NoC architectures using silicon photonics. We propose a compact structure of optical multilevel signaling link (OMLS), high bandwidth OMLS-NoC architectures, and an automated link allocation Pareto-optimization framework. The OMLS link doubles the transmission bandwidth of each waveguide by transmitting data into a 4-ASK signal. It exhibits great potential for improving bandwidth, area, and cost of optical interconnects, and for NOCs in particular. To highlight the potential advantages of OMLS for NoCs, an OMLS implementation approach is proposed to satisfy communication demands of future multicore architectures. Finally, the Pareto- optimization framework utilizes both deterministic and stochastic optimization algorithms to achieve optimal link allocations based on performance objectives, such as latency and power, to generate computer-designed NoC architectures and automate architecture design in the future.