Complex digital signal processing systems are commonly found implemented on heterogeneous networks that consist of various types of processor architectures in order to meet the demanding design and performance constraints. The design process for such systems is complicated and very time consuming. For example, one must partition the system and map the application domain onto the corresponding processing architectures to ensure the design constraints are met. This requires intricate understanding of the algorithms within the application domain and the hardware infrastructure to implement the algorithms as efficiently as possible. Therefore, in order to shorten the design and development time, a higher level of abstraction is required to manage the complexity. At the same time, rapid implementation must be employed in order to achieve design space exploration and hardware optimisation. To enable these challenges to be addressed, a high level design methodology must be developed. This thesis presents an automated system level methodology that maps digital signal processing algorithms to processor networks which include field programmable gate arrays. This work proposes a core-based, unified environment that allows a high level of abstraction to be expressed in the form of hierarchical dataflow graphs which exploit the use of intellectual property cores to leverage system level complexity. The concept of encapsulation using cores applies to both data processing and communication infrastructure of the system. A set of well defined interfaces has been developed to ensure functional behaviour of the system is completely orthogonal to the communication network fabric. The goals are seamless core integration and the ease of scalability which are crucial to implementing complex systems rapidly. In addition, a tool based on this core-based methodology has been developed which demonstrates that the whole design process can be completely automated to significantly shorten the design and development time. The tool, called "coreFlow", constitutes a set of modules which implement the concept of the core-based methodology. This work is supported by a number of examples to illustrate how the tool overcomes various complex system designs challenges, such as mapping onto multiple processors and FPGA(s), parallel and high speed serial interface implementations, the ease of channel scalability of up to 256 per FPGA, various data types and operations (scalar, vector, matrices), and the support of various data precision types. Furthermore, to assess the tool capability in implementing complex digital signal processing systems, a set of typical radar and sonar applications are used. Firstly, a beamforming sonar system is used to show the flexibility in managing systems which demand a high degree of scalability. Secondly, an adaptive beamformer system has been designed where the implementation of a complex core such as QR decomposition can be partitioned to a target FPGA based platform. This illustrates a key advantage that designers only need to focus on refining the functional specification at dataflow graph level while the lower level implementations are generated automatically.