SRAM memories constitute a considerable fraction of modern VLSI designs and consist of a single system repeated thousands of times. Thus, design of these singular bitcells is essential to optimizing SRAM performance. However, comparison of designs is often difficult due to highly variable testing conditions, making direct comparisons of systems infeasible without independent simulations. This document serves as an introduction to common SRAM metrics in the categories of delay, power, and static noise margin in a 22nm process node. Common SRAM types 6T, 8T, and 4T as well as 4T loadless, 5T, and 8T charge recycling memories are tested using these methods. These systems are compared and presented as a reference material for future designs.

A novel type of memory, 6T capacitively coupled, is presented and tested for viability and possible use cases. The memory is found to be infeasible using conventional methods, however a demonstration of its intended operation is presented.