With the 53rd commemoration of Moore's law and transistor sizing heading towards 4 nm, the number of transistors on an integrated circuit continue to double every year. However, there are many factors limiting this growth rate such as power consumption, which is a serious impediment for design of high-speed, low-power integrated circuits. In modern semiconductor manufacturing, leakage power in high-performance processors accounts for 20-30% of the total power. Power gating is one approach to reduce the power consumption of an integrated circuit by effectively disconnecting the power supply from blocks during idle mode and is commonly used in the design of commercial high-end processors and in SoC for portable applications.

In this thesis, coarse-grained power gating techniques are explored to reduce the power consumption of a fine-grained many-core processor array. This work provides a detailed analysis and comparison of the design tradeoffs between using the ring and grid methods of power gates placement. The RTL to GDSII flow was performed using Synopsys EDA tools and NanGate FreePDK45 standard open cell library. The results depict that, on a test 128-bit MAC unit, placing power gates using the grid methodology created an 8.52% less IR drop but an 8-9% congestion increase when compared to the ring methodology. The leakage power of the 128-bit MAC unit was reduced by 99.98% with both the grid and ring placement of power gates when compared to a design without power gates.