Test pattern generation and fault simulation portray the essential role for the structural testing of the Integrated Chips. Structural testing validates the correctness of a circuit in terms of gates and interconnection between gates. The primary role of structural testing is to simulate the various operations of the circuit. To simulate the circuits for the structural testing several Electronic Design Automation (EDA) tools are available for fault detection and test patterns generation. This thesis presents a new approach for fault detection and test pattern generation in the combinational circuit by using machine learning techniques. The Machine-learning model can be trained for predicting the behavioral architecture of the circuit. This machine learning model can predict the test patterns and number of possible faults by giving the inputs such as primary input and number of gates required for the circuit. In addition, a truth table of a design can be used by machine learning model to verify the functionality of a given circuit. The main purpose of this research work is to use machine learning to develop a new approach for VLSI testing and design verification of a digital logic circuit.