With the continued miniaturization of VLSI technology to sub-45 nm levels, uncertainty in nanoscale manufacturing processes and operating conditions have been found to translate into unpredictable system-level behavior of integrated circuits. As a result, there is a need for contemporary circuit simulation tools/solvers to model the forward propagation of device level uncertainty to the network response. Recently, techniques based on the robust generalized polynomial chaos (PC) theory have been reported for the uncertainty quantification of high-speed circuit, electromagnetic, and electronic packaging problems. The major bottleneck in all PC approaches is that the computational effort required to generate the metamodel scales in a polynomial fashion with the number of random input dimensions.

In order to mitigate this poor scalability of conventional PC approaches, in this dissertation, a reduced dimensional PC approach is proposed. This PC approach is based on using a high dimensional model representation (HDMR) to quantify the relative impact of each dimension on the variance of the network response. The reduced dimensional PC approach is further extended to problems with mixed aleatory and epistemic uncertainties. In this mixed PC approach, a parameterized formulation of analysis of variance (ANOVA) is used to identify the statistically significant dimensions and subsequently perform dimension reduction. Mixed problems are however characterized by far greater number of dimensions than purely epistemic or aleatory problems, thus exacerbating the poor scalability of PC expansions. To address this issue, in this dissertation, a novel dimension fusion approach is proposed. This approach fuses the epistemic and aleatory dimensions within the same model parameter into a mixed dimension. The accuracy and efficiency of the proposed approaches are validated through multiple numerical examples.