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2017
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      Cover image for New Data Structures and Algorithms for Logic Synthesis and Verification
      13. 
      Cover image for From Variability Tolerance to Approximate Computing in Parallel Integrated Architectures and Accelerators
      14. 
      Cover image for Testing of Interposer-Based 2.5D Integrated Circuits
      15. 
      Cover image for More-than-Moore 2.5D and 3D SiP Integration
      16. 
      More-than-Moore 2.5D and 3D SiP Integration
      by 
      Radojcic, Riko. author.
      http://dx.doi.org/10.1007/978-3-319-52548-8
      Format: 
      Excerpt: 
      Opportunities: 3D SiP -- More-than-Moore Design Eco-System -- More-than-Moore Adoption Landscape.
      Cover image for Handbook of Hardware/Software Codesign
      17. 
      Handbook of Hardware/Software Codesign
      by 
      Ha, Soonhoi. editor.
      http://dx.doi.org/10.1007/978-94-017-7267-9
      Format: 
      Excerpt: 
      -of-the-art techniques. Students and researchers will appreciate the wide spectrum of subjects that belong to the design
      Cover image for Designing with Xilinx® FPGAs Using Vivado
      18. 
      Designing with Xilinx® FPGAs Using Vivado
      by 
      Churiwala, Sanjay. editor.
      http://dx.doi.org/10.1007/978-3-319-42438-5
      Format: 
      Excerpt: 
      concepts, major mechanisms for design entry, and methods to realize the most efficient implementation of
      Cover image for Foundations of Hardware IP Protection
      19. 
      Foundations of Hardware IP Protection
      by 
      Bossuet, Lilian. editor.
      http://dx.doi.org/10.1007/978-3-319-50380-6
      Format: 
      Excerpt: 
      book serves as a single-source reference to design space exploration of hardware security and IP
      Cover image for Parallel Sparse Direct Solver for Integrated Circuit Simulation
      20. 
      Parallel Sparse Direct Solver for Integrated Circuit Simulation
      by 
      Chen, Xiaoming. author.
      http://dx.doi.org/10.1007/978-3-319-53429-9
      Format: 
      Excerpt: 
      This book describes algorithmic methods and parallelization techniques to design a parallel sparse
      Cover image for Embedded Software Verification and Debugging
      21. 
      Embedded Software Verification and Debugging
      by 
      Lettnin, Djones. editor.
      http://dx.doi.org/10.1007/978-1-4614-2266-2
      Format: 
      Excerpt: 
      software with hardware dependencies. Coverage includes the entire flow of design, verification and
      Cover image for Automatic Analog IC Sizing and Optimization Constrained with PVT Corners and Layout Effects
      22. 
      Automatic Analog IC Sizing and Optimization Constrained with PVT Corners and Layout Effects
      by 
      Lourenço, Nuno. author.
      http://dx.doi.org/10.1007/978-3-319-42037-0
      Format: 
      Excerpt: 
      approaches. The authors describe a methodology for an automatic flow for analog IC design, including details
      Cover image for RFID Security A Lightweight Paradigm
      23. 
      RFID Security A Lightweight Paradigm
      by 
      Khattab, Ahmed. author.
      http://dx.doi.org/10.1007/978-3-319-47545-5
      Format: 
      Excerpt: 
      accessible to a broad range of readers, enabling them to improve their RFID security design. This book also
      Cover image for Hardware Protection through Obfuscation
      24. 
      Hardware Protection through Obfuscation
      by 
      Forte, Domenic. editor.
      http://dx.doi.org/10.1007/978-3-319-49019-9
      Format: 
      Excerpt: 
      protection based on hardware obfuscation, which makes reverse-engineering an IC design infeasible for