Search Results for Processor Architectures.

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49.

Microprocessor architectures and systems : RISC, CISC, and DSP

Heath, Steve, author.

ScienceDirect https://www.sciencedirect.com/science/book/9780750600323

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Excerpt:

; System integrity; Requirements for a new processor architecture; Software compatibility; Enter the MC

50.

Supercomputers in seismic exploration

Eisner, E. (Elmer)

ScienceDirect http://www.sciencedirect.com/science/book/9780080370187

Format:

Excerpt:

Architectures with Algorithms; Optical Architectures; Conclusion; References; Chapter 6. Seismic Data Processing

51.

Selective Search Architectures and Brute Force Scan Techniques for Summarizing Social Media Posts

Wang, Yulu, author.

http://gateway.proquest.com/openurl?url_ver=Z39.88-2004&rft_val_fmt=info:ofi/fmt:kev:mtx:dissertation&res_dat=xri:pqm&rft_dat=xri:pqdiss:10744425

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Excerpt:

modern processor architectures. Where the summarization of social media posts is concerned, although

52.

High-performance embedded computing : architectures, applications, and methodologies

Wolf, Marilyn, 1958-

ScienceDirect http://www.sciencedirect.com/science/book/9780123694850

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Excerpt:

Variable-Performance CPU Architectures -- 2.6 Processor Memory Hierarchy -- 2.7 Additional CPU Mechanisms

53.

Designing SOCs with configured cores : unleashing the Tensilica Xtensa and diamond cores

Leibson, Steve.

ScienceDirect https://www.sciencedirect.com/science/book/9780123724984

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Excerpt:

basics -- 4. Basic processor configurability -- 5. MPSOC system architectures and design tools -- 6

54.

Embedded computing : a VLIW approach to architecture, compilers and tools

Fisher, Joseph A.

ScienceDirect http://www.sciencedirect.com/science/book/9781558607668

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Excerpt:

design with high-performance processor architectures, microarchitectures and compilers, and with the

55.

Network processor design. Vol. 2, Issues and practices

Franklin, Mark A., 1940-

ScienceDirect http://www.sciencedirect.com/science/book/9780121981570

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Excerpt:

Venkatachalam -- Chapter 19. Implementing QoS Mechanisms on the Motorola C-Port C-5e Network Processor, Pranav

Cover image for Algorithms and parallel VLSI architectures III : proceedings of the International Workshop, Algorithms and Parallel VLSI Architectures III, Leuven, Belgium, August 29-31, 1994

56.

Algorithms and parallel VLSI architectures III : proceedings of the International Workshop, Algorithms and Parallel VLSI Architectures III, Leuven, Belgium, August 29-31, 1994

International Workshop on Algorithms and Parallel VLSI Architectures (3rd : 1994 : Louvain, Belgium)

ScienceDirect http://www.sciencedirect.com/science/book/9780444821065

Format:

Excerpt:

-- Chapter 17. Instruction-level parallelism in asynchronous processor architectures -- Chapter 18. High

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