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      Cover image for Emerging Technology and Architecture for Big-data Analytics
      1. 
      Emerging Technology and Architecture for Big-data Analytics
      by 
      Chattopadhyay, Anupam. editor.
      http://dx.doi.org/10.1007/978-3-319-54840-1
      Format: 
      Excerpt: 
      Emerging Technology and Architecture for Big-data Analytics Chattopadhyay, Anupam. editor.
      Cover image for More-than-Moore 2.5D and 3D SiP Integration
      2. 
      More-than-Moore 2.5D and 3D SiP Integration
      by 
      Radojcic, Riko. author.
      http://dx.doi.org/10.1007/978-3-319-52548-8
      Format: 
      Excerpt: 
      manufacturing processes, associated with the 2.5D and 3D integration technologies, as well as the business and
      Cover image for Next Generation Spin Torque Memories
      3. 
      Next Generation Spin Torque Memories
      by 
      Kaushik, Brajesh Kumar. author.
      http://dx.doi.org/10.1007/978-981-10-2720-8
      Format: 
      Excerpt: 
      and discusses the outlook for this cutting-edge technology. It also describes the architectures
      Cover image for Foundations of Hardware IP Protection
      4. 
      Foundations of Hardware IP Protection
      by 
      Bossuet, Lilian. editor.
      http://dx.doi.org/10.1007/978-3-319-50380-6
      Format: 
      Excerpt: 
      in Area of Block Ciphers -- Enhancing Secure Elements – Technology and Architecture.
      Cover image for Nanometer CMOS ICs From Basics to ASICs
      5. 
      Nanometer CMOS ICs From Basics to ASICs
      by 
      J.M. Veendrick, Harry. author.
      http://dx.doi.org/10.1007/978-3-319-47597-4
      Format: 
      Excerpt: 
      disciplines of nanometer CMOS ICs, including physics, lithography, technology, design, memories, VLSI, power
      Cover image for Testing of Interposer-Based 2.5D Integrated Circuits
      6. 
      Testing of Interposer-Based 2.5D Integrated Circuits
      by 
      Wang, Ran. author.
      http://dx.doi.org/10.1007/978-3-319-54714-5
      Format: 
      Excerpt: 
      -speed interconnect testing, built-in self-test architecture, extest scheduling, and a programmable method for low