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Princeton University. Electrical Engineering. degree granting institution.

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California State University, Fullerton. Computer Engineering. degree granting institution.

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Arnold, Ken, 1958-

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North Carolina Agricultural and Technical State University. Electrical Engineering. degree granting institution.

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Cover image for On Quality-of-Service and Memory Efficiency in Heterogeneous MPSoCs

On Quality-of-Service and Memory Efficiency in Heterogeneous MPSoCs

1.

On Quality-of-Service and Memory Efficiency in Heterogeneous MPSoCs

by

Song, Yang, author.

http://gateway.proquest.com/openurl?url_ver=Z39.88-2004&rft_val_fmt=info:ofi/fmt:kev:mtx:dissertation&res_dat=xri:pqm&rft_dat=xri:pqdiss:13807034

Format:

Excerpt:

On Quality-of-Service and Memory Efficiency in Heterogeneous MPSoCs / Song, Yang, author.

Cover image for Architectural Techniques for Disturbance Mitigation in Future Memory Systems

Architectural Techniques for Disturbance Mitigation in Future Memory Systems

2.

Architectural Techniques for Disturbance Mitigation in Future Memory Systems

by

SeyedzadehDelcheh, SeyedMohammad, author.

http://gateway.proquest.com/openurl?url_ver=Z39.88-2004&rft_val_fmt=info:ofi/fmt:kev:mtx:dissertation&res_dat=xri:pqm&rft_dat=xri:pqdiss:13872154

Format:

Excerpt:

Architectural Techniques for Disturbance Mitigation in Future Memory Systems / SeyedzadehDelcheh

Cover image for Analysis of Unified Memory Performance and Protection for Concurrent Kernel Execution

Analysis of Unified Memory Performance and Protection for Concurrent Kernel Execution

3.

Analysis of Unified Memory Performance and Protection for Concurrent Kernel Execution

by

Mankad, Kartik, author.

http://gateway.proquest.com/openurl?url_ver=Z39.88-2004&rft_val_fmt=info:ofi/fmt:kev:mtx:dissertation&res_dat=xri:pqm&rft_dat=xri:pqdiss:11018239

Format:

Excerpt:

Analysis of Unified Memory Performance and Protection for Concurrent Kernel Execution / Mankad

Cover image for Access Control Mechanism in NAND Flash Memory Controller

Access Control Mechanism in NAND Flash Memory Controller

4.

Access Control Mechanism in NAND Flash Memory Controller

by

Chamala, Raveena, author. (orcid)0000-0001-5663-1977

http://gateway.proquest.com/openurl?url_ver=Z39.88-2004&rft_val_fmt=info:ofi/fmt:kev:mtx:dissertation&res_dat=xri:pqm&rft_dat=xri:pqdiss:10812249

Format:

Excerpt:

Access Control Mechanism in NAND Flash Memory Controller / Chamala, Raveena, author. (orcid)0000

Cover image for Spintronic-based Logic-in-Memory Computation for Energyaware Neuromorphic System

Spintronic-based Logic-in-Memory Computation for Energyaware Neuromorphic System

5.

Spintronic-based Logic-in-Memory Computation for Energyaware Neuromorphic System

by

Famili, Azadeh G., author.

http://gateway.proquest.com/openurl?url_ver=Z39.88-2004&rft_val_fmt=info:ofi/fmt:kev:mtx:dissertation&res_dat=xri:pqm&rft_dat=xri:pqdiss:10808989

Format:

Excerpt:

Spintronic-based Logic-in-Memory Computation for Energyaware Neuromorphic System / Famili, Azadeh G

Cover image for Data Access Optimization in Accelerator-oriented Heterogeneous Architecture through Decoupling and Memory Hierarchy Specialization

Data Access Optimization in Accelerator-oriented Heterogeneous Architecture through Decoupling and Memory Hierarchy Specialization

6.

Data Access Optimization in Accelerator-oriented Heterogeneous Architecture through Decoupling and Memory Hierarchy Specialization

by

Ham, Tae Jun, author.

http://gateway.proquest.com/openurl?url_ver=Z39.88-2004&rft_val_fmt=info:ofi/fmt:kev:mtx:dissertation&res_dat=xri:pqm&rft_dat=xri:pqdiss:10822487

Format:

Excerpt:

Memory Hierarchy Specialization / Ham, Tae Jun, author.

Cover image for Techniques for Memory-efficiency, Low-latency and High-throughput in RDMA-based Datacenter Networks and Applications

Techniques for Memory-efficiency, Low-latency and High-throughput in RDMA-based Datacenter Networks and Applications

7.

Techniques for Memory-efficiency, Low-latency and High-throughput in RDMA-based Datacenter Networks and Applications

by

Xue, Jiachen, author.

http://gateway.proquest.com/openurl?url_ver=Z39.88-2004&rft_val_fmt=info:ofi/fmt:kev:mtx:dissertation&res_dat=xri:pqm&rft_dat=xri:pqdiss:10262181

Format:

Excerpt:

Techniques for Memory-efficiency, Low-latency and High-throughput in RDMA-based Datacenter Networks

Cover image for An Environment for Accessing Remote Field-Programmable Custom Computing Machine Accelerators with Multi-Memory Banks

An Environment for Accessing Remote Field-Programmable Custom Computing Machine Accelerators with Multi-Memory Banks

8.

An Environment for Accessing Remote Field-Programmable Custom Computing Machine Accelerators with Multi-Memory Banks

by

Jadhav, Shrikant Shridhar, author.

http://gateway.proquest.com/openurl?url_ver=Z39.88-2004&rft_val_fmt=info:ofi/fmt:kev:mtx:dissertation&res_dat=xri:pqm&rft_dat=xri:pqdiss:10750895

Format:

Excerpt:

Multi-Memory Banks / Jadhav, Shrikant Shridhar, author.

Cover image for An associative memory module for data-flow processors

An associative memory module for data-flow processors

9.

An associative memory module for data-flow processors

by

Patterson, John William, author.

http://gateway.proquest.com/openurl?url_ver=Z39.88-2004&rft_val_fmt=info:ofi/fmt:kev:mtx:dissertation&res_dat=xri:pqm&rft_dat=xri:pqdiss:10867873

Format:

Excerpt:

An associative memory module for data-flow processors / Patterson, John William, author.

Cover image for Embedded controller hardware design

Embedded controller hardware design

10.

Embedded controller hardware design

by

Arnold, Ken, 1958-

ScienceDirect http://www.sciencedirect.com/science/book/9781878707529

Format:

Excerpt:

, analysis, and design -- Memory technologies and interfacing -- CPU bus interface and timing -- A detailed

Cover image for Survey of Different SRAM Variations in 22nm Process Node

Survey of Different SRAM Variations in 22nm Process Node

11.

Survey of Different SRAM Variations in 22nm Process Node

by

Petros, Peter, author.

http://gateway.proquest.com/openurl?url_ver=Z39.88-2004&rft_val_fmt=info:ofi/fmt:kev:mtx:dissertation&res_dat=xri:pqm&rft_dat=xri:pqdiss:10810035

Format:

Excerpt:

use cases. The memory is found to be infeasible using conventional methods, however a demonstration of

Cover image for Computer organization and design : the hardware/software interface

Computer organization and design : the hardware/software interface

12.

Computer organization and design : the hardware/software interface

by

Hennessy, John L.

ScienceDirect https://www.sciencedirect.com/science/book/9781483207759

Format:

Excerpt:

concepts in memory hierarchies by starting with the simplest possible cache. This book discusses as well

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