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2017
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      Cover image for Testing of Interposer-Based 2.5D Integrated Circuits
      1. 
      Testing of Interposer-Based 2.5D Integrated Circuits
      by 
      Wang, Ran. author.
      http://dx.doi.org/10.1007/978-3-319-54714-5
      Format: 
      Excerpt: 
      -speed interconnect testing, built-in self-test architecture, extest scheduling, and a programmable method for low
      Cover image for The Dark Side of Silicon Energy Efficient Computing in the Dark Silicon Era
      2. 
      The Dark Side of Silicon Energy Efficient Computing in the Dark Silicon Era
      by 
      Rahmani, Amir M. editor.
      http://dx.doi.org/10.1007/978-3-319-31596-6
      Format: 
      Excerpt: 
      Silicon Age -- Robust Application Scheduling with Adaptive Parallelism in Dark-Silicon Constrained