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      Cover image for Design and Characterization Techniques for Reliable and Secure Integrated Circuits
      1. 
      Cover image for Testing of Interposer-Based 2.5D Integrated Circuits
      2. 
      Testing of Interposer-Based 2.5D Integrated Circuits
      by 
      Wang, Ran. author.
      http://dx.doi.org/10.1007/978-3-319-54714-5
      Format: 
      Excerpt: 
      Testing of Interposer-Based 2.5D Integrated Circuits Wang, Ran. author.
      Cover image for Design of CMOS Analog Integrated Fractional-Order Circuits Applications in Medicine and Biology
      3. 
      Design of CMOS Analog Integrated Fractional-Order Circuits Applications in Medicine and Biology
      by 
      Tsirimokou, Georgia. author.
      http://dx.doi.org/10.1007/978-3-319-55633-8
      Format: 
      Excerpt: 
      Design of CMOS Analog Integrated Fractional-Order Circuits Applications in Medicine and Biology /
      Cover image for Hardware Security and Trust Design and Deployment of Integrated Circuits in a Threatened Environment
      4. 
      Hardware Security and Trust Design and Deployment of Integrated Circuits in a Threatened Environment
      by 
      Sklavos, Nicolas. editor.
      http://dx.doi.org/10.1007/978-3-319-44318-8
      Format: 
      Excerpt: 
      Hardware Security and Trust Design and Deployment of Integrated Circuits in a Threatened
      Cover image for Enabling the Internet of Things From Integrated Circuits to Integrated Systems
      5. 
      Enabling the Internet of Things From Integrated Circuits to Integrated Systems
      by 
      Alioto, Massimo. editor.
      http://dx.doi.org/10.1007/978-3-319-51482-6
      Format: 
      Excerpt: 
      Enabling the Internet of Things From Integrated Circuits to Integrated Systems / Alioto, Massimo
      Cover image for A Novel Power Integrity Modeling Method Based on Plane Pair PEEC
      6. 
      A Novel Power Integrity Modeling Method Based on Plane Pair PEEC
      by 
      Bai, Siqi, author.
      http://gateway.proquest.com/openurl?url_ver=Z39.88-2004&rft_val_fmt=info:ofi/fmt:kev:mtx:dissertation&res_dat=xri:pqm&rft_dat=xri:pqdiss:10744238
      Format: 
      Excerpt: 
      circuits. A novel modeling mothed, i.e. the plane pair PEEC method is proposed in this thesis to model the
      Cover image for From Variability Tolerance to Approximate Computing in Parallel Integrated Architectures and Accelerators
      7. 
      From Variability Tolerance to Approximate Computing in Parallel Integrated Architectures and Accelerators
      by 
      Rahimi, Abbas. author.
      http://dx.doi.org/10.1007/978-3-319-53768-9
      Format: 
      Excerpt: 
      layers of the system from circuits, architecture, to application software. These can be combined in
      Cover image for Automatic Analog IC Sizing and Optimization Constrained with PVT Corners and Layout Effects
      8. 
      Automatic Analog IC Sizing and Optimization Constrained with PVT Corners and Layout Effects
      by 
      Lourenço, Nuno. author.
      http://dx.doi.org/10.1007/978-3-319-42037-0
      Format: 
      Excerpt: 
      circuit, and on the methodologies to estimate the circuit’s performance. The discussion also includes
      Cover image for Nanometer CMOS ICs From Basics to ASICs
      9. 
      Nanometer CMOS ICs From Basics to ASICs
      by 
      J.M. Veendrick, Harry. author.
      http://dx.doi.org/10.1007/978-3-319-47597-4
      Format: 
      Excerpt: 
      CMOS integrated circuits. It includes aspects of scaling to even beyond 12nm CMOS technologies and
      Cover image for Hardware Protection through Obfuscation
      10. 
      Hardware Protection through Obfuscation
      by 
      Forte, Domenic. editor.
      http://dx.doi.org/10.1007/978-3-319-49019-9
      Format: 
      Excerpt: 
      ’s integrated circuits (ICs) and systems. The authors discuss key issues, including illegal manufacturing of ICs
      Cover image for Design of CMOS RFIC Ultra-Wideband Impulse Transmitters and Receivers
      11. 
      Design of CMOS RFIC Ultra-Wideband Impulse Transmitters and Receivers
      by 
      Nguyen, Cam. author.
      http://dx.doi.org/10.1007/978-3-319-53107-6
      Format: 
      Excerpt: 
      frontends, operating within the 3.1-10.6 GHz frequency band, using CMOS radio-frequency integrated-circuits
      Cover image for Neuro-inspired Computing Using Resistive Synaptic Devices
      12. 
      Neuro-inspired Computing Using Resistive Synaptic Devices
      by 
      Yu, Shimeng. editor.
      http://dx.doi.org/10.1007/978-3-319-54313-0
      Format: 
      Excerpt: 
      integration. This book also discusses peripheral neuron circuits design challenges and design strategies