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      Cover image for Testing of Interposer-Based 2.5D Integrated Circuits
      1. 
      Testing of Interposer-Based 2.5D Integrated Circuits
      by 
      Wang, Ran. author.
      http://dx.doi.org/10.1007/978-3-319-54714-5
      Format: 
      Excerpt: 
      Testing of Interposer-Based 2.5D Integrated Circuits Wang, Ran. author.
      Cover image for Hardware Security and Trust Design and Deployment of Integrated Circuits in a Threatened Environment
      2. 
      Hardware Security and Trust Design and Deployment of Integrated Circuits in a Threatened Environment
      by 
      Sklavos, Nicolas. editor.
      http://dx.doi.org/10.1007/978-3-319-44318-8
      Format: 
      Excerpt: 
      Hardware Security and Trust Design and Deployment of Integrated Circuits in a Threatened
      Cover image for Professional embedded arm development
      3. 
      Professional embedded arm development
      by 
      Langbridge, James A.
      Click to View
      Format: 
      Excerpt: 
      Integrated circuits.
      Cover image for Digital system design : use of microcontroller
      4. 
      Digital system design : use of microcontroller
      by 
      Dawoud, Shenouda Dawoud.
      Click to View
      Format: 
      Excerpt: 
      Digital integrated circuits.
      Cover image for Network processor design : issues and practices
      5. 
      Network processor design : issues and practices
      by 
      Crowley, Patrick, 1974-
      ScienceDirect http://www.sciencedirect.com/science/book/9781558608757
      Format: 
      Excerpt: 
      Application-specific integrated circuits.
      Cover image for Zzaap! : taming ESD, RFI, and EMI
      6. 
      Zzaap! : taming ESD, RFI, and EMI
      by 
      Corp, M. Bruce.
      ScienceDirect http://www.sciencedirect.com/science/book/9780121899301
      Format: 
      Excerpt: 
      't supposed to be there or, worst of all, cause the sudden failure of critical integrated circuits. M. Bruce
      Cover image for From Variability Tolerance to Approximate Computing in Parallel Integrated Architectures and Accelerators
      7. 
      From Variability Tolerance to Approximate Computing in Parallel Integrated Architectures and Accelerators
      by 
      Rahimi, Abbas. author.
      http://dx.doi.org/10.1007/978-3-319-53768-9
      Format: 
      Excerpt: 
      layers of the system from circuits, architecture, to application software. These can be combined in
      Cover image for Automatic Analog IC Sizing and Optimization Constrained with PVT Corners and Layout Effects
      8. 
      Automatic Analog IC Sizing and Optimization Constrained with PVT Corners and Layout Effects
      by 
      Lourenço, Nuno. author.
      http://dx.doi.org/10.1007/978-3-319-42037-0
      Format: 
      Excerpt: 
      circuit, and on the methodologies to estimate the circuit’s performance. The discussion also includes
      Cover image for Hardware Protection through Obfuscation
      9. 
      Hardware Protection through Obfuscation
      by 
      Forte, Domenic. editor.
      http://dx.doi.org/10.1007/978-3-319-49019-9
      Format: 
      Excerpt: 
      ’s integrated circuits (ICs) and systems. The authors discuss key issues, including illegal manufacturing of ICs
      Cover image for Neuro-inspired Computing Using Resistive Synaptic Devices
      10. 
      Neuro-inspired Computing Using Resistive Synaptic Devices
      by 
      Yu, Shimeng. editor.
      http://dx.doi.org/10.1007/978-3-319-54313-0
      Format: 
      Excerpt: 
      integration. This book also discusses peripheral neuron circuits design challenges and design strategies
      Cover image for Carbon Nanotubes for Interconnects Process, Design and Applications
      11. 
      Carbon Nanotubes for Interconnects Process, Design and Applications
      by 
      Todri-Sanial, Aida. editor.
      http://dx.doi.org/10.1007/978-3-319-29746-0
      Format: 
      Excerpt: 
      -of-the-art on exploiting carbon nanotubes for interconnects for both 2D and 3D integrated circuits. Provides a