List of Figures. -- List of Tables. -- List of Examples. -- Preface. -- Acknowledgement. -- Trademarks. -- I. VHDL CODING -- 1. Introduction. -- 2. VHDL Simulation and Synthesis Flow. -- 3. Synthesizable Code for Basic Logic Components. -- 4. Signal Versus Variable. -- 5. Examples of Complex Synthesizable Code. -- 6. Pipeline Microcontroller Synthesizable Design. -- II. LOGIC SYNTHESIS WITH SYNOPSYS. -- 7. Timing Considerations in Design. -- 8. VHDL Synthesis with Timing Constraints. -- 9. GTECH Instantiation. -- 10. DesignWare Library. -- 11. Testability Issues in Synthesis. -- 12. FPGA Synthesis. -- 13. Synthesis Links to Layout. -- 14. Design Guideline to Follow for Efficient Synthesis. -- 15. Appendix A (STD_LOGIC_1164 Library). -- 16. Appendix B (Shifter Synthesis Results). -- 17. Appendix C (Counter Synthesis Results). -- 18. Appendix D (Pipeline Microcontroller Synthesis Results--Top-Down Compilation). -- 19. Appendix E (EDIF File of Synthesized Microcontroller Example from Chapter 6). -- 20. Appendix F (SDF File from Synthesized Microcontroller Example of Chapter 6). -- Glossary. -- Bibliography. -- Index.