Recent advances in process technology have enabled semiconductor manufacturers to produce ICs with minimum feature dimensions of less than 1 micron. This shrinkage in feature size has led to a massive increase in the number of devices that can be integrated onto a single chip. However, the fall in pin to gate ratios and the complexity of modern ICs has made it increasingly difficult to verify the fault free operation of both single ICs and whole systems. Multi-level Differential Current Mode Logic (MDCML) is an advanced bipolar logic family particularly suited to high speed designs and is currently employed by GEC-Plessey Semiconductors in their 'DV' range of gate arrays. This thesis investigates the particular test requirements of MDCML designs and DV arrays. The physical failure modes of bipolar circuits are investigated to ascertain the most appropriate fault model for MDCML circuits. A simple MDCML buffer is simulated at the component level to investigate the gate level effects of physical fault mechanisms. The description of differential signals and complex gates are then considered with respect to designing test patterns and obtaining efficient fault simulation. Different test schemes are then assessed for use within DV arrays. One method, Circular Self Test, is applied to a complex, high speed MDCML design. This test scheme is included and controlled within a framework of the IEEE 1149.1 boundary scan architecture.