The focus of this thesis is the design, implementation, and simulation of hardware to improve the performance of a star identification procedure known as the Lost-In-Space Algorithm (LISA). Star Tracker space navigational systems employ star identification algorithms to determine the orientation of a given space vehicle. It includes an optical device that captures a potential star pattern that is then forwarded to a LISA-based software code. The software then processes the centroids, then calculates and extracts a range of star identification records originating from a Star Catalog. This thesis presents a hardware design to process the data to improve the performance. The hardware solution was developed based on the scenario where three potential stars are captured by the Star Tracker. The hardware design presented in this thesis is to be incorporated into a Field Programmable Gate Array (FPGA) by means of Computer Aided Design (CAD) software. The CAD tool used to model and implement the design is the Xilinx Integrated Synthesis Environment (ISE) and the circuit modules are created using the Verilog Hardware Description Language (HDL).

The hardware model consists of a data path and a control circuit. The essential devices within the datapath are the register files. The datapath was built using a bottom-up approach. The ultimate goal in designing the hardware was to create the ability to make simultaneous parallel comparisons between large data sets. The design was kept simple since inevitably the complexity of the circuit will increase. Although a small model was built, it served to prove that the concept is viable and that this achievement is worthy of further development. Furthermore, with the CAD tool, the simulation was conducted and the correctness of the design was verified by utilizing various scenarios.