This thesis focuses on small-grain silicon-based TFTs for high-resolution flat panel displays (FPDs) and system-on-panel (SoP) applications. Firstly, different kinds of treatments are applied to small-grain polycrystalline silicon (poly-Si) thin film transistors (TFTs) to generate high-performance device characteristics. Then, the reliability of small-grain poly-Si TFTs is systematically characterized and studied. Last, self-aligned top-gate microcrystalline ( muc-Si) TFTs are fabricated and investigated.

For the performance improvement of small-grain poly-Si TFTs, firstly, small-grain poly-Si TFTs integrating a high-k gate dielectric with bridged-grain (BG) active channel are demonstrated. The as-fabricated devices exhibit outstanding performance improvements, especially for off-state characteristics. Then, two-dimensional dot-array (DA) doping technology is proposed to improve device performance. With the DA doping in the active channel, device characteristics show great improvements, especially for on-state characteristics. Last, a simple method is introduced to grow thermal SiO2 interlayer between small-grain poly- Si channel and the high-k gate dielectric for high-performance small-grain poly-Si TFTs. The effect of the buffer layer, O2 annealing and the Si interstitials is clarified. All these treatments on small-grain poly-Si TFTs are low-temperature compatible, low cost, and without process variation and reliability issues. Small-grain poly-Si TFTs employing these treatments show great potential in high-resolution FPDs and SoP applications.

For reliability test, firstly, water-related parasitic effect in poly-Si TFTs is systematically studied. The role of H2O in the interface during negative bias temperature instability (NBTI) stress is clarified. Different combinations of passivation layers are applied to poly-Si TFTs to keep H 2O from diffusing into the gate oxide network near interface, and the NBTI reliability is effectively improved. Secondly, degradation of BG poly-Si TFTs under different kinds of DC stresses is characterized. Compared to normal poly-Si TFTs, BG poly-Si TFTs exhibit better hot carrier (HC) reliability, better self-heating (SH) reliability and better NBTI reliability. Lateral electric field (Ex) reduction at drain side, improved Joule heat diffusion at channel length direction and boron-hydrogen bond formation in the channel are respectively responsible for these improvements. Thirdly, AC-drain/gate-stress induced degradation in poly-Si TFTs is systemically investigated. A physical non-equilibrium junction degradation model including time-dependent carrier emission/recombination process is proposed. The dynamic HC degradation in BG poly-Si TFTs is greatly alleviated due to Ex reduction caused by the sharing of the field across multiple reverse biased junctions. Lastly, device degradation under "practical" stress is systematically studied in poly-Si TFTs. Under either the "driving" stress or "switching" stress, BG poly-Si TFTs show much more stable performance compared to normal poly-Si TFTs. Based on the test results and simulation results, the non-equilibrium junction degradation model is further developed. All test results indicate BG poly-Si TFTs have great potential in high-resolution FPDs and SoP applications.

For muc-Si TFTs, firstly, the muc-Si film deposition conditions and doping methods are investigated. Then, self-aligned top-gate muc-Si TFTs are fabricated and characterized. By replacing high-temperature silicon dioxide (SiO2) with low-temperature SiO2, the performance of muc-Si TFT can be greatly improved due to the prevention of hydrogen diffusion to the air. Lastly, the BG structure is successfully applied to the self-aligned top-gate muc-Si TFTs. By employing the BG structure, the device performance is further improved.