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Novel low-power design methodology for high speed linear re-drivers
Başlık:
Novel low-power design methodology for high speed linear re-drivers
Yazar:
Nguyen, Hieu, author.
ISBN:
9780438006614
Yazar Ek Girişi:
Fiziksel Tanımlama:
1 electronic resource (107 pages)
Genel Not:
Source: Dissertation Abstracts International, Volume: 79-10(E), Section: B.
Advisors: Martin Margala.
Özet:
With the data rate transmission increases across all wireline communication protocols such as USB, HDMI, and PCIe; it becomes more and more challenging for PCB designers to route high speed signal and achieve acceptable signal integrity to pass compliance testing. As the insertion loss of the channel grows exponentially with high speed data transmission (> 5Gb/s), any of extra routing or mismatch impedance could add losses to the transmission line and degrade the signal integrity. It is further exacerbated as chip processors nowadays tend to use small signal swing for low power purpose.
To address these challenges, this thesis presents a high speed, low power and programmable linear re-driver that compensates for the signal losses while amplifying the signal swing. First, the thesis describes design blocks of linear re-drivers, the suitable order of the design blocks, and the combination between equalization and amplification to best match with the compensation for the signal losses. Second, an analog design methodology using lookup plots is introduced to optimize transistor sizing for a balance between speed and power efficiency. This methodology can be applied to any technology without understanding details of device SPICE models. Third, a forward scaling technique is proposed to overcome the challenges with driving the heavy loading by the output driver of the linear re-driver while giving the benefits of ratio-based design in mass production. In addition, it helps designers choose the optimal number of stages in the design to meet design specifications; exploit the best performance out of a CMOS technology. Finally, a proportional to absolute temperature (PTAT) biasing scheme is utilized to combat temperature variation, significantly minimize the specification's variation across extreme temperatures (i.e. -20°C and 85°C). To prove the proposed design methodology, a re-driver test chip is fabricated in a low-cost CMOS 180nm technology. A testing framework in USB 3.1 (5 Gb/s) gen 1 is followed to evaluate the re-driver's performance. Comparing to prior arts, the re-driver's power consumption is only half as much as other re-driver in the market; while giving wider range of compensation and amplification.
Notlar:
School code: 0111
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Yer Numarası | Demirbaş Numarası | Shelf Location | Lokasyon / Statüsü / İade Tarihi |
---|---|---|---|
XX(683999.1) | 683999-1001 | Proquest E-Tez Koleksiyonu | Arıyor... |
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