Search Results for Logic design.

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Introduction to Logic Circuits & Logic Design with VHDL

LaMeres, Brock J. author.

http://dx.doi.org/10.1007/978-3-319-34195-8

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Introduction to Logic Circuits & Logic Design with VHDL LaMeres, Brock J. author.

Introduction to Logic Circuits & Logic Design with Verilog

LaMeres, Brock J. author.

http://dx.doi.org/10.1007/978-3-319-53883-9

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Introduction to Logic Circuits & Logic Design with Verilog LaMeres, Brock J. author.

New Data Structures and Algorithms for Logic Synthesis and Verification

Amaru, Luca Gaetano. author.

http://dx.doi.org/10.1007/978-3-319-43174-1

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Logic design.

Fundamentals of Electronic Systems Design

Lienig, Jens. author.

http://dx.doi.org/10.1007/978-3-319-55840-0

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Logic design.

Separation Logic for High-level Synthesis

Winterstein, Felix. author.

http://dx.doi.org/10.1007/978-3-319-53222-6

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Logic design.

From Variability Tolerance to Approximate Computing in Parallel Integrated Architectures and Accelerators

Rahimi, Abbas. author.

http://dx.doi.org/10.1007/978-3-319-53768-9

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Logic design.

Testing of Interposer-Based 2.5D Integrated Circuits

Wang, Ran. author.

http://dx.doi.org/10.1007/978-3-319-54714-5

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Logic design.

Linear circuit design handbook

Zumbahlen, Hank.

ScienceDirect http://www.sciencedirect.com/science/book/9780750687034

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COMPUTERS -- Logic Design.

Electronics for Embedded Systems

Bindal, Ahmet. author.

http://dx.doi.org/10.1007/978-3-319-39439-8

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-of-the-art CMOS logic family and its interface with older logic families such as TTL, sensors and sensor physics

10.

Non-logic Devices in Logic Processes

Ma, Yanjun. author.

http://dx.doi.org/10.1007/978-3-319-48339-9

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Process -- Part 2. Non-Logic Device Design in Logic Processes -- 4. Non-logic MOSFETs in Logic CMOS

11.

Fundamentals of IP and SoC Security Design, Verification, and Debug

Bhunia, Swarup. editor.

http://dx.doi.org/10.1007/978-3-319-50057-7

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Protection Techniques -- A Systematic Approach to Fault-Attack Resistant Design -- Hardware Trojan Attacks

12.

Computer-Aided Design of Microfluidic Very Large Scale Integration (mVLSI) Biochips Design Automation, Testing, and Design-for-Testability

Hu, Kai. author.

http://dx.doi.org/10.1007/978-3-319-56255-1

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-contamination removal; Presents a design-for-testability (DfT) technique that can achieve 100% fault coverage at the

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