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      Cover image for System-on-chip test architectures : nanometer design for testability
      1. 
      Cover image for System-on-chip test architectures nanometer design for testability
      2. 
      System-on-chip test architectures nanometer design for testability
      by 
      Wang, Laung-Terng.
      Click to View
      Format: 
      Excerpt: 
      Touba, Nur A.
      Cover image for VLSI test principles and architectures : design for testability
      3. 
      VLSI test principles and architectures : design for testability
      by 
      Wang, Laung-Terng, editor.
      ScienceDirect https://www.sciencedirect.com/science/book/9780123705976
      Format: 
      Excerpt: 
      , Kuen-Jong Lee, and Nur A. Touba -- Logic diagnosis / Shi-Yu Huang -- Memory testing and built-in self
      Cover image for Electronic design automation : synthesis, verification, and test
      4. 
      Electronic design automation : synthesis, verification, and test
      by 
      Wang, Laung-Terng.
      ScienceDirect http://www.sciencedirect.com/science/book/9780123743640
      Format: 
      Excerpt: 
      of CMOS design / Xinghao Chen and Nur A. Touba -- Ch. 3. Design for testability / Laung-Terng Wang